1. Field of the Invention
The present invention relates to a capacitor in a semiconductor device, and more particularly to a capacitor in a semiconductor device and a method for fabricating the same capable of improving leakage current and breakdown voltage characteristics.
2. Description of the Prior Art
As generally known in the art, the cell size of semiconductor memory devices decreases as they become more highly integrated. Therefore, it is difficult to secure a capacitance of a capacitor adequate for the maintenance of the memory device characteristics as uniformly as required, since the area of the capacitor decreases due to the decrease of the cell size.
For example, in the case of a highly integrated device above the 64 M DRAM level, the cell size has been seriously reduced following the increase of the degree of integration. As a result, it is impossible to secure capacitance of a capacitor adequate for the activation of the cell with the conventional capacitor structure as required.
Accordingly, with regard to the recent highly integrated devices, electric charge storage electrodes have been formed in various three-dimensional structures to secure desired amounts of capacitance of a capacitor as above, or high dielectric ratio materials have been employed as dielectric layer materials, or the dielectric layer have been deposited thin at the maximum.
These are because the capacitance for a capacitor is directly proportional to the surface area of the electrode and the dielectric ratio of the dielectric layer and inversely proportional to the interval between an upper electrode and a lower electrode, i.e., the approximate thickness of the dielectric layer.
In this regard, lower electrodes have been fabricated in a cylindrical structure, a concave structure, or a pin structure to increase the surface area of the electrodes and thereby increasing the capacitance for a capacitor; high dielectric ratio materials such as Ta2O5 or BST have been employed as the dielectric materials to increase the capacitance for a capacitor; and a thin layer consisting of multiple layers of N/O (nitride/oxide) have been employed to increase the capacitance for a capacitor by reducing the thickness of the dielectric layer.
However, in the case of employing high dielectric ratio materials to increase the capacitance for a capacitor, due to limitations on decreasing the thickness of the dielectric layer, several problems have been incurred as follows.
In particular, in the cases of employing N/O multi-layers or employing high dielectric materials such as Ta2O5 or BST as dielectric layer materials, recent technologies have confronted limitations in the treatment of interfaces between the lower electrode and the dielectric layer. Therefore, the capacitance of a capacitor can be increased through using the N/O multi-layers or high dielectric materials such as Ta2O5 or BST as dielectric materials while also decreasing the thickness of the dielectric layer. However, leakage current and breakdown voltage characteristics, etc., deteriorate due to inferiority of the interfaces between the lower electrode and the dielectric layer, resulting in reduction of reliability and production yield.
As described above, at the present stage of development in employing N/O multi-layers or high dielectric materials such as Ta2O5 or BST as dielectric layer materials, such materials cause a decrease of reliability and production yield, so it is difficult to apply them in order to increase the capacitance of a capacitor in the semiconductor device.
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a capacitor in a semiconductor device and a method for fabricating the same capable of preventing the deterioration of leakage current and breakdown voltage characteristics by using N/O multi-layers or high dielectric materials such as Ta2O5 or BST as dielectric layer materials.
In order to accomplish this object, there is provided a capacitor in a semiconductor device, comprising: a lower electrode made of doped silicon materials formed on a semiconductor substrate; a thin silicon nitride layer formed on the lower electrode; a silicon oxynitride layer formed on the surface of the silicon nitride layer through oxidation of the silicon nitride layer; a dielectric layer formed on the silicon oxynitride layer; and an upper electrode formed on the dielectric layer.
In the above capacitor, the lower electrode is formed of any one structure selected from a group composed of a plate structure, a cylindrical structure, a concave structure, and a pin structure, and is formed to have a hemispherical silicon grain on the surface thereof.
Also, the silicon nitride layer is formed to a thickness of 5 to 30 xc3x85 and the silicon oxynitride layer is formed to have a thickness of under 15 xc3x85 from the surface of the silicon nitride layer.
Further, the dielectric layer is made of N/O or Ta2O5.
In order to accomplish this object, there is also provided a method for fabricating a capacitor in a semiconductor device, comprising the steps of: forming a lower electrode made of doped silicon materials on a semiconductor substrate; depositing a thin silicon nitride layer on the lower electrode; forming a silicon oxynitride layer on the surface of the silicon nitride layer through oxidation of the silicon nitride layer; depositing a dielectric layer on the silicon oxynitride layer; and forming an upper electrode on the dielectric layer.
In the above method, the lower electrode is formed of any one structure selected from a group composed of a plate structure, a cylindrical structure, a concave structure, and a pin structure, and is formed to have a hemispherical silicon grain on the surface thereof.
Also, the step of depositing a thin silicon nitride layer is performed through any one process selected from a group composed of a plasma NH3 nitridation process, a thermal NH3 nitridation process, and an LPCVD process, and the silicon nitride layer is deposited to a thickness of 5 to 30 xc3x85.
In accordance with the embodiment of the present invention, the oxidation of the silicon nitride layer is performed through any one process selected from a group composed of a plasma enhanced oxidation, a low pressure oxidation, an atmosphere pressure oxidation, and a natural air cooling at an atmosphere of O2, and is performed to form the silicon nitric oxide layer to a thickness of below 15 xc3x85 from the surface of the silicon nitride layer.
Further, in the above method, the dielectric layer is made of N/O or Ta2O5, and the post treatment of the dielectric layer is performed through a heat treatment using O2, N2, or N/O.
Also, in the above method, a post treatment of the deposited dielectric layer using any one gas selected from the group composed of O2, N2, and NO, is performed prior to forming the upper electrode and after depositing the dielectric layer.
In accordance with the method of the present invention, the steps of depositing the silicon nitride layer, oxidizing the silicon nitride layer, depositing the dielectric layer, and performing post treatment of the dielectric layer are carried out in an in-situ or no time delay manner.